SPI control register
| DUMMY_OUT | In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. |
| FADDR_DUAL | Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. |
| FADDR_QUAD | Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. |
| FCMD_DUAL | Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. |
| FCMD_QUAD | Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. |
| FREAD_DUAL | In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. |
| FREAD_QUAD | In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. |
| Q_POL | The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. |
| D_POL | The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. |
| HOLD_POL | SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. |
| WP_POL | Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. |
| RD_BIT_ORDER | In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. |
| WR_BIT_ORDER | In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. |